Phase locked loop having DC bias circuitry

ABSTRACT

A phase locked loop (PLL) circuit is provided having a DC biasing circuit that enables the PLL to operate with a single power supply voltage, and which also eliminates the dead zone associated with the phase detector of the PLL. The PLL includes a phase detector for detecting the phase difference between a reference clock signal and a feedback signal and for generating phase pulse outputs corresponding to this phase difference, an integrator coupled to the phase pulse outputs for generating a phase voltage in proportion to the pulse width of the phase pulse outputs, and a voltage controlled oscillator coupled to the phase voltage for generating a local oscillator signal that is synchronized to the reference clock signal and which is coupled to the feedback signal. The DC biasing circuit generates a variable pulse width bias signal that is merged with the phase pulse outputs in order to polarize the integrator inputs at a particular DC bias level. In a first embodiment, the DC biasing circuit merges the variable pulse width bias signal with both positive and negative phase outputs from the phase detector in order to polarize the integrator. In a second embodiment, the DC biasing circuit merges the variable pulse width bias signal with only one of the positive or the negative phase outputs from the phase detector in order to simultaneously polarize the integrator and to eliminate the dead zone associated with the phase detector by injecting a continuous phase error into the PLL feedback signal.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention is directed to the field of phase locked loops. More specifically, the invention provides an improved phase locked loop (“PLL”) that includes a DC bias circuit. The DC bias circuit enables the PLL to operate using a single supply voltage, and also may be used to eliminate the phase discrimination “dead zone” normally associated with the phase detector element of the PLL.

2. Description of the Related Art

Phase locked loops are well-known elements in analog and digital circuit design. A phase locked loop operates by receiving an external reference clock signal and generating a localized oscillator signal that is synchronized with the external reference clock signal. The local oscillator signal may operate at the same frequency as the reference clock signal or at some integer multiple of that frequency. A general description of the theory and operational characteristics of a PLL is contained in Couch, Digital and Analog Communication Systems, Fourth Edition, pp. 289-296.

FIG. 1 is a circuit diagram of a known PLL circuit 10. This circuit 10 includes four primary elements—a phase detector 14, an operational amplifier 26, a voltage controlled oscillator (VCXO) 32, and a counter 36. This circuit 10 generates a local oscillator signal (PLL clock) 34 that is synchronized with an external reference clock signal 12, but which operates at a higher frequency than the external reference clock 12. This is accomplished by feeding back a divided down version 38 of the local oscillator signal 34 to the phase detector 14, which then compares the phases of the reference clock signal 12 with the feedback signal 38.

The phase detector 14 is preferably a phase frequency detector, and has two inputs and two outputs. The two inputs of the phase detector 14 are coupled to the external reference clock signal 12 and the PLL feedback signal 38, and the two outputs 16A, 16B are coupled to the operational amplifier 26. If the PLL feedback signal 38 leads in phase with respect to the reference clock signal 12, then the phase detector 14 outputs a pulse on the negative phase output (ph−) 16A. Similarly, if the reference clock signal 12 leads in phase with respect to the PLL feedback signal 38, then the phase detector 14 outputs a pulse on the positive phase output (ph+) 16B. These output pulses on the positive and negative phase outputs 16A, 16B from the phase detector 14 are characterized by a pulse width that is equivalent to the phase difference between the two inputs.

When the phase difference between the reference clock signal 12 and the PLL feedback signal 38 is nearly zero degrees (i.e., when the PLL is “locked”), then the phase detector enters an operational region in which it cannot discriminate the phase difference between the two input signals. This operational region is referred to herein as the “dead zone.” As the phase difference of the two inputs approaches zero degrees, the phase detector 14 outputs minimum-width pulses on both the positive and negative phase outputs 16A, 16B.

The phase detector outputs 16A, 16B are coupled to the operational amplifier 26 through a pair of RC circuits. These RC circuits configure the operational amplifier 26 as an integrator. The negative phase output (ph−) 16A is coupled to the negative input of the operational amplifier 26 through the RC circuit composed of resistors 18, 28 and capacitor 30. And the positive phase output (ph+) 16B is coupled to the positive input of the operational amplifier 26 through the RC circuit composed of resistors 20, 22 and capacitor 24.

This integrator 18-30 receives the pulses from the phase detector outputs (ph+, ph−) 16A, 16B and generates a voltage level at its output that is proportional to the pulse width of the phase pulses. This phase voltage is then provided as an input to the voltage controlled oscillator (VCXO) 32. Because these phase pulses are typically very narrow, particularly when the reference clock signal 12 is very nearly in phase with the PLL feedback signal 38, the voltage output of the operational amplifier is typically near ground. For this reason, the operational amplifier 26 is typically powered using two power supply voltages, such as +/−12 volts or +/−15 volts. This is done because the operational amplifier 26 output becomes non-linear as the output voltage approaches the power supply rails. Thus, it does not operate effectively from a single supply voltage, such as +5V, where the other supply rail is ground, since the phase voltage is typically very close to ground when the PLL is in the locked condition.

The voltage controlled oscillator 32 generates an output clock signal, PLL clock 34, which is characterized by a frequency that is proportional to the phase voltage from the integrator. This clock signal, PLL clock 34, is the localized oscillator signal that is synchronized with the external reference clock 12. The PLL clock signal 34 is then fed back to one of the inputs of the phase detector 14 either directly, or via a counter 36.

The counter 36 is configured as a divide-by-N counter, and it generates the PLL feedback signal 38, which is a frequency divided version of the PLL clock signal 34. By selecting an appropriate value of N, a circuit designer can select the frequency of the PLL clock signal 34 with respect to the external reference clock 12. For example, if the circuit designer desires to generate a synchronized version of the reference clock signal 12, but at a frequency 10 times greater than the reference clock signal 12, then the value of N would be 10.

FIG. 2 is a timing diagram showing the operation of the PLL set forth in FIG. 1. This timing diagram sets forth, from top to bottom, the PLL clock signal 34, the reference clock signal 12, the PLL feedback signal 38, and the corresponding phase pulse signals on the positive and negative phase outputs 16B, 16A of the phase detector 14. As seen in this diagram, during normal operation (i.e., when the PLL is locked), the PLL clock signal 34 is in phase with the reference clock 12, but at a higher frequency. The PLL feedback signal 38 is nearly identical to the external reference clock signal 12 when the circuit is locked, and is in phase with this signal. When locking occurs, the phase difference between the PLL feedback signal 38 and the reference clock signal 12 is very small, and the phase detector 14 enters the “dead zone” region in which it cannot further discriminate between the phase difference of the two input signals 12, 38. In this region, the phase detector 14 outputs two extremely narrow pulses at the positive and negative phase outputs 16B, 16A, during the rising edge of the input clocks 12, 38.

The circuit shown in FIG. 1 suffers from two problems. The first problem relates to the dead zone. As described above, at some point during the locking of the PLL, the phase difference between the reference clock signal 12 and the feedback signal 38 becomes so small that the phase detector 14 cannot determine which signal is leading or lagging the other signal. This dead zone region thus presents a minimum threshold phase difference below which the PLL cannot properly lock. Although the characteristics of the phase detector circuitry 14 generally determine the extent of the dead zone region, the minimum threshold difference represented by this region may also be affected by component variations and tolerances in the external RC elements 18-24, 28-30 of the integrator.

The second problem with the circuit shown in FIG. 1 relates to the operational amplifier 26 power scheme. As described above, because the positive and negative phase outputs 16A, 16B of the phase detector 14 are typically very narrow pulses, particularly as the PLL approaches a locked condition, the output voltage of the integrator circuit is typically near zero volts (ground). Because of this very small output voltage, and also because an operational amplifier does not exhibit linear characteristics near its power rails, this requires that the operational amplifier 26 is powered using a plus/minus power supply scheme, such as +/−15 volts. This presents a problem when the apparatus in which the PLL circuit 10 is employed includes only a single power supply, such as +5V.

Therefore, there remains a need in this field for an improved PLL circuit that overcomes the problems noted herein.

SUMMARY OF THE INVENTION

A phase locked loop (PLL) circuit is provided having a DC biasing circuit that enables the PLL to operate with a single power supply voltage, and which also eliminates the dead zone associated with the phase detector of the PLL. The PLL includes a phase detector for detecting the phase difference between a reference clock signal and a feedback signal and for generating phase pulse outputs corresponding to this phase difference, an integrator coupled to the phase pulse outputs for generating a phase voltage in proportion to the pulse width of the phase pulse outputs, and a voltage controlled oscillator coupled to the phase voltage for generating a local oscillator signal that is synchronized to the reference clock signal and which is coupled to the feedback signal. The DC biasing circuit generates a variable pulse width bias signal that is merged with the phase pulse outputs in order to polarize the integrator inputs at a particular DC bias level. In a first embodiment, the DC biasing circuit merges the variable pulse width bias signal with both positive and negative phase outputs from the phase detector in order to polarize the integrator. In a second embodiment, the DC biasing circuit merges the variable pulse width bias signal with only one of the positive or the negative phase outputs from the phase detector in order to simultaneously polarize the integrator and to eliminate the dead zone associated with the phase detector by injecting a continuous phase error into the PLL feedback signal.

According to one aspect of the invention, a phase locked loop is provided. The phased lock loop includes: (1) a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; (2) an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; (3) a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; (4) a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and (5) a DC offset pulse generator for polarizing the positive and negative inputs of the operational amplifier so that the operational amplifier can operate using a single power supply voltage.

According to another aspect of the invention, an improved phase locked loop is provided having a phase detector for comparing a reference signal with a feedback signal and for generating phase pulses having a pulse width corresponding to the phase difference between the reference signal and the feedback signal, an integrator coupled to the phase pulses for generating a voltage level corresponding to the pulse width of the phase pulses, wherein the integrator includes an operational amplifier having positive and negative inputs, and a voltage controlled oscillator coupled to the voltage level for generating the feedback signal. The improvement includes a DC offset pulse generator for biasing the positive and negative inputs of the operational amplifier so that the operational amplifier can operate from a single power supply voltage.

Still another aspect of the invention provides a phase locked loop, comprising: (1) means for detecting the phase difference between a reference clock signal and a feedback signal; (2) means for generating a phase voltage corresponding to the phase difference between the reference clock signal and the feedback signal; (3) means for generating the feedback signal, wherein the feedback signal is characterized by a frequency that varies in proportion to the phase voltage; and (4) means for biasing the means for generating the phase voltage such that the means for generating the phase voltage can operate from a single power supply.

Another aspect of the invention provides an improved phase locked loop having a phase detector, a voltage controlled oscillator, and at least one operational amplifier coupled between the phase detector and the voltage controlled oscillator, wherein the operational amplifier includes a positive input and a negative input. The improvement includes a DC offset pulse generator coupled to at least one of the positive or the negative inputs of the operational amplifier, wherein the DC offset pulse generator generates a digital pulse signal that polarizes the inputs of the operational amplifier so that the operational amplifier can operate using a single power supply voltage.

Still another aspect of the invention provides a phase locked loop circuit, comprising: (1) a phase detector coupled to a reference signal and a feedback signal that generates a positive phase pulse output if the phase of the feedback signal lags the reference signal and that generates a negative phase pulse output if the phase of the feedback signal leads the reference signal; (2) an integrator coupled to the phase detector for generating a phase voltage in proportion to the pulse width of either the positive or the negative phase pulse output; (3) a voltage controlled oscillator coupled to the phase voltage for generating a local oscillator signal that is synchronized in phase with the reference signal; (4) a feedback circuit for coupling the local oscillator signal to the feedback signal; and (5) a biasing circuit for merging a bias pulse signal with at least one of the positive or negative phase pulse outputs in order to polarize the integrator so that it can operate using a single power supply voltage.

It should be noted that these are just some of the many aspects of the present invention. Other aspects not specified will become apparent upon reading the detailed description of the drawings set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a known PLL;

FIG. 2 is a timing diagram showing the operation of the PLL set forth in FIG. 1;

FIG. 3 is a circuit diagram of a first embodiment of a PLL according to the present invention;

FIG. 4 is a timing diagram showing the operation of the PLL set forth in FIG. 3;

FIG. 5 is a circuit diagram of a second embodiment of a PLL according to the present invention; and

FIG. 6 is a timing diagram showing the operation of the PLL set forth in FIG. 5.

DETAILED DESCRIPTION OF THE DRAWINGS

Turning now to the remaining drawing figures, FIG. 3 is a circuit diagram of a first embodiment of a PLL circuit 10 according to the present invention. Similar to the circuit shown in FIG. 1, this circuit 10 includes a phase detector 14, an integrator 18-30, a voltage controlled oscillator 32, and a counter 36 configured as a divider. The operation of these elements is similar to that described with reference to FIG. 1. In addition, however, the circuit shown in FIG. 3 includes a DC bias circuit coupled to the forward and feedback paths of the PLL 10. The DC bias circuit is preferably a digitally controlled circuit that includes a DC offset pulse circuit 40 and a pair of OR-gates 42A, 42B.

The DC offset pulse circuit 40 is configured in parallel with the counter 36, and preferably generates a variable-width digital pulse signal 44 that is centered 180 degrees out of phase with the PLL clock signal 34. By configuring the digital pulse signal 44 in this manner, the impact on the phase detector's 14 linearity is minimized. The digital pulse signal 44 is provided to one of the inputs of each of the OR-gates 42A, 42B. Coupled to the other inputs of the respective OR-gates 42A, 42B are the positive and negative phase outputs of the phase detector 14. The OR-gates merge the two signals at their inputs, thus providing an OR function. The outputs of the OR-gates 16A, 16B are therefore the positive and negative phase outputs of the phase detector 14 integrated with the digital pulse signal 44.

One purpose of merging the digital pulse signal 44 with the positive and negative phase outputs 16A, 16B of the phase detector is to polarize the +/− inputs of the operational amplifier 26 of the integrator. As noted above, in the known PLL circuit (as shown in FIG. 1), the operational amplifier requires a +/− power supply scheme in order to provide a linear output signal around zero volts. In the circuit shown in FIG. 3, however, by simultaneously integrating a digital pulse signal 44 into the phase detector outputs, the operational amplifier inputs are polarized (or biased) to a particular DC bias level based upon the width of the digital pulse signal 44. Because of the common-mode rejection ratio of the operational amplifier 26, this common-mode DC bias presented to both inputs of the operational amplifier 26 will essentially be ignored. Thus, the digital pulse signal 44 has no effect on the locking operation of the PLL. Because the operational amplifier 26 inputs have been pre-biased to a particular voltage level above ground, however, the operational amplifier 26 no longer requires a +/− power supply and can operate on a single supply voltage.

For example, a single +5V DC power supply can now be utilized to power the operational amplifier 26. The other power rail of the operational amplifier 26 can then be coupled to ground. By varying the pulse width of the digital pulse signal 44, the operational amplifier can be polarized to a particular voltage level. The amount of polarization is proportional to the width of the digital pulse signal 44 in comparison to the width of the reference clock signal 12. Thus, if the pulse width of the digital pulse signal 44 is half the pulse width of the reference clock signal 12, and the power supply for the operational amplifier is +5V DC, then the operational amplifier inputs will be polarized at +2.5V DC. This digital pulse signal 44 is variable, however, and thus the circuit designer can polarize the operational amplifier 26 inputs to any bias level between the power supply rails, as necessary. This polarization scheme ensures that even for very narrow pulse outputs from the phase detector 14, the operational amplifier 26 is operating in a linear region.

FIG. 4 is a timing diagram showing the operation of the PLL 10 set forth in FIG. 3. This timing diagram shows the PLL clock 24, the external reference clock 12, the PLL feedback signal 38, the digital pulse signal 44 from the DC offset pulse circuit 40, and the positive and negative phase outputs 16A, 16B of the phase detector 14 merged with the digital pulse signal 44 (i.e., the outputs of the two OR-gates 42A, 42B.) This timing diagram is very similar to that shown in FIG. 2, particularly on the rising edge of the reference clock signal 12. Like FIG. 2, this timing diagram depicts the operation of the PLL 10 when it is in the locked condition and the phase difference between the reference clock signal 12 and the PLL feedback signal 38 is minimized. At the rising edge of the external reference clock 38, the phase pulse outputs 16A, 16B are similar to those shown in FIG. 2, and include a minimal pulse output representative of the phase detector being locked but in the dead zone region where it cannot further discriminate the phase difference between the two input signals.

At the falling edge of the external reference clock 12, however, FIG. 4 is substantially different than FIG. 2. Here, instead of simply presenting a ground signal at the phase detector outputs 16A, 16B, the circuit shown in FIG. 3 merges the digital pulse signal 44 with the phase detector outputs in order to generate the polarization levels for the operational amplifier 26. These polarization pulses on 16A, 16B are then coupled to the inputs of the operational amplifier 26 and bias the operational amplifier to a DC voltage level in proportion to the ratio of the pulse width of the digital pulse signal 44 to the pulse width of the reference clock 12. In this manner, the operational amplifier 26 can operate using a single power supply voltage, and yet can linearly integrate the very narrow pulses output from the phase detector 14 on the rising edge of the reference clock 12.

FIG. 5 is a circuit diagram of a second embodiment of a PLL according to the present invention. In addition to addressing the dual power supply problem for the operational amplifier 26, the circuit shown in FIG. 5 also addresses the problem of the dead zone of the phase detector 14. The circuit in FIG. 5 is identical to the circuit in FIG. 3, except that the digital pulse signal 44 from the DC offset circuit +40 is only merged with one of the outputs from the phase detector 14. Here, it is shown that the digital pulse signal 44 is merged with the positive phase output 16B of the phase detector 14. Alternatively, it could be merged with the negative phase output 16A.

Initially, this would appear to disrupt the concept of polarizing the inputs of the operational amplifier 26, because the digital pulse signal 44 is only being applied to the positive input of the operational amplifier 26. But because the PLL includes a feedback loop, the circuit will sense the digital pulse signal 44 on the positive phase output 16B, and will attempt to compensate for this apparent phase difference by generating a corresponding digital pulse signal on the negative phase output 16A, thus providing the other polarization pulse for the operational amplifier's 26 negative input. In this manner, both polarization pulses can be generated and applied to the inputs of the operational amplifier 26 using only a single digital pulse 44 integrated with just one of the phase detector outputs 16A, 16B.

FIG. 6 is a timing diagram showing the operation of the PLL set forth in FIG. 5. This timing diagram shows the PLL clock signal 34, the reference clock signal 12, the PLL feedback signal 38, the digital pulse signal 44, and the positive and negative phase output signals 16A, 16B. Here, the positive phase output signal 16B results from the OR-ing of the positive output from the phase detector 14 and the digital pulse signal 44.

As shown in this figure, the PLL 10 has locked with a continuous phase error equivalent to the pulse width of the digital pulse signal 44. Because the digital pulse signal 44 is a multiple of the PLL clock signal 34, however, the phase error between the PLL clock signal 34 and the reference clock 12 is zero degrees when the PLL is locked. The digital pulse signal 44 from the DC offset circuit 40 is injected into the positive phase output signal 16B on the falling edge of the PLL feedback signal 38, as previously, but now the digital pulse signal 44 is injected into the negative phase output signal 16A on the rising edge of the PLL feedback signal 38, due to the configuration of the feedback loop.

By configuring the PLL 10 in the manner shown in FIG. 5, the problem of the “dead zone” in the phase detector 14 is eliminated. This occurs because the PLL feedback signal 38 is always out of phase from the reference clock signal 12 by the pulse width of the digital pulse signal 44. When the PLL is locked, the phase difference between the PLL feedback signal 38 and the reference clock signal 12 is no longer zero degrees, thus eliminating the “dead zone” effect in the prior art PLL where the phase difference is near zero degrees when the PLL is locked. This enables the PLL shown in FIG. 5 to discriminate phase differences at a much lower threshold than in the prior art circuit shown in FIG. 1.

The preferred embodiments described with reference to the drawing figures are presented only to demonstrate examples of the invention. This detailed description is not meant to limit the invention in any way. Additional, and/or alternative, embodiments of the invention would be apparent to one of ordinary skill in the art upon reading this disclosure. 

What is claimed is:
 1. A phase locked loop, comprising: a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and a DC offset pulse generator for polarizing the positive and negative inputs of the operational amplifier so that the operational amplifier can operate using a single power supply voltage, wherein the DC offset pulse generator comprises a DC offset pulse generation circuit for generating a DC offset pulse, and circuitry for merging the DC offset pulse with the positive and negative phase detection signals, thereby polarizing the positive and negative inputs of the operational amplifier.
 2. The phase locked loop of claim 1, wherein the integrator further includes at least two RC circuits coupled to the operational amplifier, a first RC circuit coupled to the positive phase detection signal, and a second RC circuit coupled to the negative phase detection signal.
 3. The phase locked loop of claim 1, wherein the feedback circuit is a direct electrical connection between the local oscillator signal and the feedback signal.
 4. The phase locked loop of claim 1, wherein the feedback circuit includes a divider for generating the feedback signal by dividing the frequency of the local oscillator signal.
 5. The phase locked loop of claim 1, wherein the divider is characterized by a division ratio N, where N is an integer that corresponds to the desired frequency of the local oscillator signal in comparison to the reference clock signal.
 6. The phase locked loop of claim 1, wherein the division ration N is adjustable.
 7. The phase locked loop of claim 1, wherein the DC offset pulse has a predetermined pulse width.
 8. The phase locked loop of claim 7, wherein the DC offset pulse generator is coupled to the local oscillator signal and generates the DC offset pulse using the local oscillator signal.
 9. The phase locked loop of claim 8, wherein the DC offset pulse is centered 180 degrees out of phase from the local oscillator signal.
 10. The phase locked loop of claim 7, wherein the pulse width of the DC offset pulse is variable.
 11. The phase locked loop of claim 10, wherein the pulse width of the DC offset pulse is varied using a digital variation signal.
 12. The phase locked loop of claim 1, wherein the DC offset pulse generation circuit is coupled to the local oscillator signal for generating the DC offset pulse based on the local oscillator signal, wherein the DC offset pulse is centered 180 degrees out of phase from the local oscillator signal.
 13. The phase locked loop of claim 1, wherein the circuitry for merging includes two OR gates, a first OR gate for merging the DC offset pulse with the positive phase detection signal, and a second OR gate for merging the DC offset pulse with the negative phase detection signal.
 14. The phase locked loop of claim 1, wherein the pulse width of the DC offset pulse is variable.
 15. The phase locked loop of claim 14, wherein the polarization level of the positive and negative inputs of the operational amplifier is proportional to the pulse width of the DC offset pulse.
 16. A phase locked loop, comprising: a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and a DC offset pulse generator for polarizing the positive and negative inputs of the operational amplifier so that the operational amplifier can operate using a single power supply voltage; wherein the phase detector is characterized by a phase discrimination dead zone within which the phase detector cannot discriminate between the phase difference between the reference clock signal and the feedback signal, the DC offset pulse generator further comprising: a DC offset pulse generator circuit for generating a DC offset pulse having a predetermined pulse width; and circuitry for merging the DC offset pulse with one of the positive or the negative phase detection signals, thereby injecting a phase difference into the feedback signal in relation to the reference clock signal such that the dead zone of the phase detector is eliminated.
 17. The phase locked loop of claim 16, wherein the circuitry for merging includes an OR gate.
 18. An improved phase locked loop having a phase detector, a voltage controlled oscillator, and at least one operational amplifier coupled between the phase detector and the voltage controlled oscillator, wherein the operational amplifier includes a positive input and a negative input, the improvement comprising: a DC offset pulse generator coupled to at least one of the positive or the negative inputs of the operational amplifier, wherein the DC offset pulse generator generates a digital pulse signal that polarizes the inputs of the operational amplifier so that the operational amplifier can operate using a single power supply voltage, wherein the phase detector receives an external reference signal and a feedback signal and generates positive and negative phase output signals depending on the phase difference between the reference clock signal and the feedback signal, the DC offset pulse generator further comprising: a pulse generator for generating the digital pulse signal; and a pair of OR gates, each OR gate having two inputs and one output, wherein one of the inputs of each OR gate is coupled to the pulse signal from the pulse generator, the other inputs to the OR gates are couples to the positive and negative phase output signals from the phase detector, and the outputs of the OR gates are coupled to the positive and negative inputs of the operational amplifier.
 19. The improved phase locked loop of claim 18, wherein the digital pulse signal is characterized by a variable pulse width.
 20. The improved phase locked loop of claim 19, wherein the level of polarization of the operational amplifier corresponds to the pulse width of the digital pulse signal.
 21. A phase locked loop circuit, comprising: A phase detector coupled to a reference signal and a feedback signal that generates a positive phase pulse output if the phase of the feedback signal lags the reference signal and that generates a negative phase pulse output if the phase of the feedback signal leads the reference signal; an integrator coupled to the phase detector for generating a phase voltage in proportion to the pulse width of either the positive or the negative phase pulse output; a voltage controlled oscillator coupled to the phase voltage for generating a local oscillator signal that is synchronized in phase with the reference signal; a feedback circuit for coupling the local oscillator signal to the feedback signal; and a biasing circuit for merging a bias pulse signal with at least one of the positive or negative phase pulse outputs in order to polarize the integrator so that it can operate using a single power supply voltage, wherein the biasing circuit includes a DC offset pulse generator for generating the bias pulse signal and at least one logic gate for merging the bias pulse signal with one of the positive or negative phase pulse outputs.
 22. The phase locked loop of claim 21, wherein the integrator includes an operational amplifier having two inputs, one input being coupled to the positive phase pulse output and the other input being coupled to the negative phase pulse output.
 23. The phase locked loop of claim 21, wherein the feedback circuit is a direct connection between the local oscillator signal and the feedback signal.
 24. The phase locked loop of claim 21, wherein the feedback circuit is a divider.
 25. The phase locked loop of claim 21, wherein the biasing circuit is coupled to the local oscillator signal.
 26. The phase locked loop of claim 25, wherein the bias pulse signal is centered 180 degrees out of phase from the local oscillator signal.
 27. The phase locked loop of claim 21, wherein the bias pulse signal is characterized by a variable pulse width.
 28. The phase locked loop of claim 21, wherein the pulse width of the bias pulse signal sets the polarization level of the integrator.
 29. An improved phase locked loop of the kind having a phase detector for generating positive and negative phase detection signals and an integrator coupled to the phase detector, the integrator having positive and negative inputs, the improvement comprising: a DC offset pulse generator for generating a DC offset pulse; and circuitry for merging the DC offset pulse with the positive and negative phase detection signals, thereby polarizing the positive and negative inputs of the integrator.
 30. The improved phase locked loop of claim 29, wherein the circuitry for merging includes two logic gates, a first logic gate for merging the DC offset pulse with the positive phase detection signal, and a second logic gate for merging the DC offset pulse with the negative phase detection signal.
 31. The improved phase locked loop of claim 30, wherein the first and second logic gates are OR gates.
 32. The improved phase locked loop of claim 29, wherein the pulse width of the DC offset pulse is variable.
 33. The improved phase locked loop of claim 32, wherein the polarization level of the positive and negative inputs of the integrator is proportional to the pulse width of the DC offset pulse.
 34. The improved phase locked loop of claim 29, wherein the circuitry for merging includes at least one logic gate for merging the DC offset pulse with either the positive phase detection signal or the negative phase detection signal.
 35. The improved phase locked loop of claim 34, wherein the at least one logic gate is an OR gate. 